Aldec Releases Riviera 2003.03 with New Support for SystemC and Increased Performance

Henderson Nevada, April 1st, 2003 -- Aldec, Inc., a pioneer in mixed language simulation and advanced design tools for FPGA and ASIC devices, announced today the release of Riviera 2003.03 with increased performance, new debugging features and introduced support for SystemC. The Riviera product is based on Aldec’s industry-proven VHDL and Verilog mixed-language simulation technology used by ASIC and high-density FPGA designers who want to use new generation system-on-chip methodologies.

Increased Performance
Riviera’s optimized simulation compiler reduces compilation time by as much as 50% over previous versions. More efficient memory allocation in Riviera substantially reduces the amount of memory required during both compilation and simulation, further accelerating overall run times.

“Riviera 2003.03 has not only focused on increased compilation performance and better memory handling, but has also added several new and improved debugging capabilities and support for SystemC,” stated Eric Seabrook, Product Marketing Manager for Aldec, adding, “this release reaches a new level of performance and functionality for ASIC and SoC designers.”

SystemC Support
In addition to VHDL, Verilog and mixed HDL simulation in Riviera, Aldec has added the ability to co-simulate SystemC in version 2003.03. Riviera’s co-simulation support is especially useful for the growing number of system-level designs incorporating C components and testbenches. Results of both RTL and C simulation can be viewed and modified in Riviera’s Waveform Viewer/Editor for simulation analysis and modification.

Improved Debugging
Riviera now includes Toggle Coverage and Assertion support as part of its expansive debugging suite. Both features offer more detailed information about the design and help designers improve the overall quality of the code. Riviera 2003.03 includes Toggle Coverage and Assertion support as part of its Standard Edition for no additional cost.

Hardware Acceleration
The hardware acceleration version of Riviera, Riviera-IPT, now includes an enhanced Design Verification Manger (DVM) with project management to control which modules stay in software and which are off-loaded to hardware for faster verification runs; this hardware/software co-verification process offers designers a completely integrated platform for simulation acceleration.

Partner Interface
Riviera 2003.03 includes an improved, interactive interface to Summit Design’s Visual Elite 3.0, including its new Cause & Effect feature; as well as an enhanced interface to Novas Debussy with updated FSDB writer and overall VHPI/PLI optimization.

Availability
Riviera 2003.03 is available today based on a floating O/S independent license that supports UNIX, Windows and Linux. It includes an industry-proven mixed VHDL and Verilog simulation engine that supports IEEE VHDL 1076-87/93 and Vital 2000 in addition to Verilog 1376-95 and 2001. Riviera is a comprehensive verification tool and includes Code Coverage, Design Profiler and interfaces to other EDA tools for no additional cost. Riviera is sold directly by Aldec in the U.S. and authorized international distributors. A FREE evaluation copy of Riviera, go to www.aldec.com/riviera.

About Aldec
Aldec, Inc., an 18-year EDA tool provider, is committed to delivering high-performance, HDL-based design verification software for UNIX, Linux and Windows platforms. Aldec is dedicated and responsive to serving its customers’ needs with its offices located around the globe. Continuous innovation, superior product quality and total commitment to customer service comprise the foundation of Aldec’s strategic objectives. Additional information about Aldec is available at http://www.aldec.com.

Riviera and Riviera-IPT are trademarks of Aldec, Inc. All other trademarks or registered trademarks are property of their respective owners

Contact:        
Eric Seabrook        
Aldec, Inc.
(702) 990-4400 ext. 224        
erics@aldec.com